This invention relates to an address selecting circuitry and more particularly to the address selection for a semiconductor memory device using insulated-gate field effect transistors (hereafter referred to simply as FETs).
In a conventional semiconductor memory device, e.g. a random-access memory having 4096 memory cells (hereafter referred to simply as 4KRAM), disclosed in, for example, FIGS. 1, 3 and 5 of U.S. Pat. No. 3,969,706 specification, 6-bit row address and 6-bit column address data is supplied to six address input pins, each address input pin is connected with row and column address buffer circuits each of which receives an address input signal A.sub.i of TTL (Transistor-Transistor Logic) level to produce true and complement signals a.sub.i and a.sub.1 of MIS or MOS level, and these signals a.sub.i and a.sub.i are used to drive row and column decoders for the selection of a particular memory cell. In such a 4KRAM, there must be provided two address buffer circuits (for row address selection and column address selection) for every address input pin so that the address buffer circuits to be used totals 12 (6 .times. 2 = 12). The provision of a large number of address buffer circuits would encounter the following problems. Namely, too much power would be consumed in the case where a RAM has a larger capacity. The integration density of circuits cannot be improved. The input capacity at the address input pin becomes large. Erroneous operations such as erroneous address selection are liable to be caused due to the accompanying increase in the number of peripheral circuits so that the reliability is poor.